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A new pointer-based instruction queue design and its power-performance evaluation

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10.1109/ICCD.2005.12
 
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hdl:2117/104598

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Ramírez, Marco A
Cristal Kestelman, AdriánMés informacióMés informació
Veidenbaum, Alexander V
Villa, Luis
Valero Cortés, MateoMés informacióMés informacióMés informació
Document typeConference report
Defense date2005
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.
CitationRamírez, M., Cristal, A., Veidenbaum, A.V., Villa, L., Valero, M. A new pointer-based instruction queue design and its power-performance evaluation. A: IEEE International Conference on Computer Design. "2005 International Conference on Computer Design: 02-05 October 2005 San Jose, California: proceedings". San Jose, California: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 647-653. 
URIhttp://hdl.handle.net/2117/104598
DOI10.1109/ICCD.2005.12
ISBN0-7695-2451-6
Publisher versionhttp://ieeexplore.ieee.org/document/1524220/
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