A new pointer-based instruction queue design and its power-performance evaluation
Visualitza/Obre
Cita com:
hdl:2117/104598
Tipus de documentText en actes de congrés
Data publicació2005
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i
industrial corresponents. Sense perjudici de les exempcions legals existents, queda prohibida la seva
reproducció, distribució, comunicació pública o transformació sense l'autorització del titular dels drets
Abstract
Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointer-based design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, 5GHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.
CitacióRamírez, M., Cristal, A., Veidenbaum, A.V., Villa, L., Valero, M. A new pointer-based instruction queue design and its power-performance evaluation. A: IEEE International Conference on Computer Design. "2005 International Conference on Computer Design: 02-05 October 2005 San Jose, California: proceedings". San Jose, California: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 647-653.
ISBN0-7695-2451-6
Versió de l'editorhttp://ieeexplore.ieee.org/document/1524220/
Fitxers | Descripció | Mida | Format | Visualitza |
---|---|---|---|---|
01524220.pdf | 28,87Mb | Visualitza/Obre |