Hierarchical clustered register file organization for VLIW processors
Tipus de documentText en actes de congrés
EditorIEEE Computer Society
Condicions d'accésAccés obert
Technology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned into components so that most of the communication is done locally. In this paper, we propose a novel register file organization for VLIW cores that combines clustering with a hierarchical register file organization. Functional units are organized in clusters, each one with a local first level register file. The local register files are connected to a global second level register file, which provides access to memory. All intercluster communications are done through the second level register file. This paper also proposes MIRS-HC, a novel modulo scheduling technique that simultaneously performs instruction scheduling, cluster selection, inserts communication operations, performs register allocation and spill insertion for the proposed organization. The results show that although more cycles are required to execute applications, the execution time is reduced due to a shorter cycle time. In addition, the combination of clustering and hierarchy provides a larger design exploration space that trades-off performance and technology requirements.
CitacióZalamea, F., Llosa, J., Ayguadé, E., Valero, M. Hierarchical clustered register file organization for VLIW processors. A: IEEE International Parallel and Distributed Processing Symposium. "Proceedings of the 17th International Parallel&Distributed Processing Symposium". Nice: IEEE Computer Society, 2003, p. 1-10.
Versió de l'editorhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1213178&tag=1