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Quantifying the benefits of SPECint distant parallelism in simultaneous multithreading architectures

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Ortega Fernández, Daniel
Martel Pérez, Iván
Krishnan, Venkata
Ayguadé Parra, EduardMés informacióMés informacióMés informació
Valero Cortés, MateoMés informacióMés informacióMés informació
Document typeConference report
Defense date1999
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
We exploit the existence of distant parallelism that future compilers could detect and characterise its performance under simultaneous multithreading architectures. By distant parallelism we mean parallelism that cannot be captured by the processor instruction window and that can produce threads suitable for parallel execution in a multithreaded processor. We show that distant parallelism can make feasible wider issue processors by providing more instructions from the distant threads, thus better exploiting the resources from the processor in the case of speeding up single integer applications. We also investigate the necessity of out-of-order processors in the presence of multiple threads of the same program. It is important to notice at this point that the benefits described are totally orthogonal to any other architectural techniques targeting a single thread.
CitationOrtega, D., Martel, I., Krishnan, V., Ayguadé, E., Valero, M. Quantifying the benefits of SPECint distant parallelism in simultaneous multithreading architectures. A: International Conference on Parallel Architectures and Compilation Techniques. "1999 International Conference on Parallel Architectures and Compilation Techniques: October 12-16, 1999, Newport Beach, California: proceedings". Newport Beach, California: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 117-124. 
URIhttp://hdl.handle.net/2117/103783
DOI10.1109/PACT.1999.807436
ISBN0-7695-0425-6
Publisher versionhttp://ieeexplore.ieee.org/document/807436/
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