Access to vectors in multi-module memories
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnection network degrades the performance of computers. Address transformation schemes, such as interleaving, skewing and linear transformations, have been proposed to achieve conflict-free access for streams with constant stride. However, this is achieved only for some strides. In this paper, we summarize a mechanism to request the elements in an out-of-order way which allows to achieve conflict-free access for a larger number of strides. We study the cases of a single vector processor and of a vector multiprocessor system. For this latter case, we propose a synchronous mode of accessing memory that can be applied in SIMD machines or in MIMD systems with decoupled access and execution.
CitacióValero, M., Peiron, M., Ayguadé, E. Access to vectors in multi-module memories. A: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. "Second Euromicro Workshop on Parallel and Distributed Processing: proceedings". Málaga: Institute of Electrical and Electronics Engineers (IEEE), 1994, p. 228-236.
Versió de l'editorhttp://ieeexplore.ieee.org/document/592494/