| dc.contributor.author | Espasa Sans, Roger |
| dc.contributor.author | Valero Cortés, Mateo |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2017-04-06T10:15:49Z |
| dc.date.available | 2017-04-06T10:15:49Z |
| dc.date.issued | 1997-09 |
| dc.identifier.citation | Espasa, R., Valero, M. Exploiting instruction-and data-level parallelism. "IEEE micro", Setembre 1997, vol. 17, núm. 5, p. 20-27. |
| dc.identifier.issn | 0272-1732 |
| dc.identifier.uri | http://hdl.handle.net/2117/103411 |
| dc.description.abstract | Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications. |
| dc.format.extent | 8 p. |
| dc.language.iso | eng |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Parallel processing (Electronic computers) |
| dc.subject.other | Vector processor systems |
| dc.subject.other | Performance evaluation |
| dc.title | Exploiting instruction-and data-level parallelism |
| dc.type | Article |
| dc.subject.lemac | Processament en paral·lel (Ordinadors) |
| dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| dc.identifier.doi | 10.1109/40.621210 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/document/621210/ |
| dc.rights.access | Open Access |
| local.identifier.drac | 654274 |
| dc.description.version | Postprint (published version) |
| local.citation.author | Espasa, R.; Valero, M. |
| local.citation.publicationName | IEEE micro |
| local.citation.volume | 17 |
| local.citation.number | 5 |
| local.citation.startingPage | 20 |
| local.citation.endingPage | 27 |
