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dc.contributor.authorEspasa Sans, Roger
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-04-06T10:15:49Z
dc.date.available2017-04-06T10:15:49Z
dc.date.issued1997-09
dc.identifier.citationEspasa, R., Valero, M. Exploiting instruction-and data-level parallelism. "IEEE micro", Setembre 1997, vol. 17, núm. 5, p. 20-27.
dc.identifier.issn0272-1732
dc.identifier.urihttp://hdl.handle.net/2117/103411
dc.description.abstractSimultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.
dc.format.extent8 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherVector processor systems
dc.subject.otherPerformance evaluation
dc.titleExploiting instruction-and data-level parallelism
dc.typeArticle
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/40.621210
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/621210/
dc.rights.accessOpen Access
local.identifier.drac654274
dc.description.versionPostprint (published version)
local.citation.authorEspasa, R.; Valero, M.
local.citation.publicationNameIEEE micro
local.citation.volume17
local.citation.number5
local.citation.startingPage20
local.citation.endingPage27


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