Exploiting instruction-and data-level parallelism

Espasa Sans, Roger; Valero Cortés, Mateo

doi:10.1109/40.621210

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Espasa Sans, Roger

Valero Cortés, Mateo

Document typeArticle

Defense date1997-09

Rights accessOpen Access

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder

Abstract

Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.

CitationEspasa, R., Valero, M. Exploiting instruction-and data-level parallelism. "IEEE micro", Setembre 1997, vol. 17, núm. 5, p. 20-27.

URIhttp://hdl.handle.net/2117/103411

DOI10.1109/40.621210

ISSN0272-1732

Publisher versionhttp://ieeexplore.ieee.org/document/621210/

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