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dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorMartínez, José F
dc.contributor.authorLlosa Espuny, José Francisco
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationCristal, A., Martínez, J., Llosa, J., Valero, M. A case for resource-conscious out-of-order processors. "IEEE computer architecture letters", Desembre 2003, vol. 2, núm. 1, p. 1-4.
dc.description.abstractModern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures.
dc.format.extent4 p.
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors -- Design and construction
dc.subject.otherOut-of-order processor
dc.subject.otherMemory latency
dc.subject.otherInstruction-level parallelism
dc.subject.otherResource utilization
dc.titleA case for resource-conscious out-of-order processors
dc.subject.lemacMicroprocessadors -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
local.citation.authorCristal, A.; Martínez, J.; Llosa, J.; Valero, M.
local.citation.publicationNameIEEE computer architecture letters

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