Show simple item record

dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorMartínez, José F
dc.contributor.authorLlosa Espuny, José Francisco
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-03-30T13:01:03Z
dc.date.available2017-03-30T13:01:03Z
dc.date.issued2003-12
dc.identifier.citationCristal, A., Martínez, J., Llosa, J., Valero, M. A case for resource-conscious out-of-order processors. "IEEE computer architecture letters", Desembre 2003, vol. 2, núm. 1, p. 1-4.
dc.identifier.issn1556-6056
dc.identifier.urihttp://hdl.handle.net/2117/103112
dc.description.abstractModern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures.
dc.format.extent4 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors -- Design and construction
dc.subject.otherOut-of-order processor
dc.subject.otherMemory latency
dc.subject.otherInstruction-level parallelism
dc.subject.otherResource utilization
dc.subject.otherCheckpointing
dc.titleA case for resource-conscious out-of-order processors
dc.typeArticle
dc.subject.lemacMicroprocessadors -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/L-CA.2003.4
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1650121/
dc.rights.accessOpen Access
drac.iddocument654709
dc.description.versionPostprint (published version)
upcommons.citation.authorCristal, A., Martínez, J., Llosa, J., Valero, M.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE computer architecture letters
upcommons.citation.volume2
upcommons.citation.number1
upcommons.citation.startingPage1
upcommons.citation.endingPage4


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder