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dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorLarriba Pey, Josep
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-03-30T09:58:24Z
dc.date.available2017-03-30T09:58:24Z
dc.date.issued2005-01
dc.identifier.citationRamírez, A., Larriba, J., Valero, M. Software trace cache. "IEEE transactions on computers", Gener 2005, vol. 54, núm. 1, p. 22-35.
dc.identifier.issn0018-9340
dc.identifier.urihttp://hdl.handle.net/2117/103093
dc.description.abstractWe explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture in order to increase fetch performance. The Software Trace Cache (STC) is a code layout algorithm with a broader target than previous layout optimizations. We target not only an improvement in the instruction cache hit rate, but also an increase in the effective fetch width of the fetch engine. The STC algorithm organizes basic blocks into chains trying to make sequentially executed basic blocks reside in consecutive memory positions, then maps the basic block chains in memory to minimize conflict misses in the important sections of the program. We evaluate and analyze in detail the impact of the STC, and code layout optimizations in general, on the three main aspects of fetch performance; the instruction cache hit rate, the effective fetch width, and the branch prediction accuracy. Our results show that layout optimized, codes have some special characteristics that make them more amenable for high-performance instruction fetch. They have a very high rate of not-taken branches and execute long chains of sequential instructions; also, they make very effective use of instruction cache lines, mapping only useful instructions which will execute close in time, increasing both spatial and temporal locality.
dc.format.extent14 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCache memory
dc.subject.lcshCompilers (Computer programs)
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherPipeline processors
dc.subject.otherInstruction fetch
dc.subject.otherCompiler optimizations
dc.subject.otherBranch prediction
dc.subject.otherTrace cache
dc.titleSoftware trace cache
dc.typeArticle
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. DAMA-UPC - Data Management Group
dc.identifier.doi10.1109/TC.2005.13
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1362637/
dc.rights.accessOpen Access
local.identifier.drac654996
dc.description.versionPostprint (published version)
local.citation.authorRamírez, A.; Larriba, J.; Valero, M.
local.citation.publicationNameIEEE transactions on computers
local.citation.volume54
local.citation.number1
local.citation.startingPage22
local.citation.endingPage35


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