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dc.contributor.authorOuerdani, Imen
dc.contributor.authorDagbagi, Mohamed
dc.contributor.authorBen Abdelghani, Afef Bennani
dc.contributor.authorSlama-Belkhodja, Ilhem
dc.contributor.authorMontesinos Miracle, Daniel
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Elèctrica
dc.date.accessioned2017-03-24T11:55:27Z
dc.date.available2017-03-24T11:55:27Z
dc.date.issued2017-01-01
dc.identifier.citationOuerdani, I., Dagbagi, M., Ben Abdelghani, A., Slama-Belkhodja, I., Montesinos-Miracle, D. Phase opposition disposition PWM strategy and hardware in the loop validation for a 3-SM modular multilevel converter. "Journal of electrical systems", 1 Gener 2017, vol. 13, núm. 1, p. 1-15.
dc.identifier.issn1112-5209
dc.identifier.urihttp://hdl.handle.net/2117/102868
dc.description.abstractThis paper focuses on the carrier disposition Pulse Width Modulation (PWM) strategies for Modular Multilevel Converters (MMC). The authors propose a new Phase Opposition Disposition PWM (PODPWM) scheme applicable regardless of the converter’s sub-modules number. Moreover, a capacitor voltage sorting algorithm is synthesized aiming to ensure the converter’s balanced operation. Simulation re sults of a 3.6 MVA, 3-SM-MMC are presented and discussed. In addition, a Hardware In the Loop (HIL) validation of the proposed PODPWM has been made using Field Programmable Gate Array (FPGA) target. The actual power system (the 3-SM-MMC and the 3-phase RL load) is then replaced by its real-time emulator. The latter is interfaced to the PODPWM control under test and both are implemented and run altogether in the same Xilinx XC7Z020 Zynq FPGA device. The obtained real-time HIL emulation results are presented and compared to the offline simulation results.
dc.format.extent15 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria mecànica::Processos de fabricació mecànica
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshPower electronics
dc.subject.lcshMachinery
dc.subject.otherModular multilevel converter
dc.subject.otherPulse Width Modulation
dc.subject.otherCirculating current
dc.subject.otherActive balance
dc.subject.otherReal-time Emulator
dc.subject.otherHardware In the Loop
dc.titlePhase opposition disposition PWM strategy and hardware in the loop validation for a 3-SM modular multilevel converter
dc.typeArticle
dc.subject.lemacElectrònica de potència
dc.subject.lemacMaquinària
dc.contributor.groupUniversitat Politècnica de Catalunya. CITCEA - Centre d'Innovació Tecnològica en Convertidors Estàtics i Accionaments
dc.relation.publisherversionhttp://journal.esrgroups.org/jes/papers/13_1_1.pdf
dc.rights.accessOpen Access
local.identifier.drac19809692
dc.description.versionPostprint (published version)
local.citation.authorOuerdani, I.; Dagbagi, M.; Ben Abdelghani, A.; Slama-Belkhodja, I.; Montesinos-Miracle, D.
local.citation.publicationNameJournal of electrical systems
local.citation.volume13
local.citation.number1
local.citation.startingPage1
local.citation.endingPage15


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Attribution-NonCommercial-NoDerivs 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain