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Explaining dynamic cache partitioning speed ups
dc.contributor.author | Moretó Planas, Miquel |
dc.contributor.author | Cazorla, Francisco |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-03-23T12:23:33Z |
dc.date.available | 2017-03-23T12:23:33Z |
dc.date.issued | 2007-01 |
dc.identifier.citation | Moreto, M., Cazorla, F., Alex Ramirez, Valero, M. Explaining dynamic cache partitioning speed ups. "IEEE computer architecture letters", Gener 2007, vol. 6, núm. 1, p. 1-4. |
dc.identifier.issn | 1556-6056 |
dc.identifier.uri | http://hdl.handle.net/2117/102823 |
dc.description.abstract | Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors |
dc.subject.lcsh | Cache memory |
dc.subject.other | Microprocessor chips |
dc.subject.other | Cache storage |
dc.title | Explaining dynamic cache partitioning speed ups |
dc.type | Article |
dc.subject.lemac | Microprocessadors |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/L-CA.2007.3 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/4278824/ |
dc.rights.access | Open Access |
local.identifier.drac | 654946 |
dc.description.version | Postprint (published version) |
local.citation.author | Moreto, M.; Cazorla, F.; Ramirez, Alex; Valero, M. |
local.citation.publicationName | IEEE computer architecture letters |
local.citation.volume | 6 |
local.citation.number | 1 |
local.citation.startingPage | 1 |
local.citation.endingPage | 4 |
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