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dc.contributor.authorMoreto Planas, Miquel
dc.contributor.authorCazorla, Francisco
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-03-23T12:23:33Z
dc.date.available2017-03-23T12:23:33Z
dc.date.issued2007-01
dc.identifier.citationMoreto, M., Cazorla, F., Alex Ramirez, Valero, M. Explaining dynamic cache partitioning speed ups. "IEEE computer architecture letters", Gener 2007, vol. 6, núm. 1, p. 1-4.
dc.identifier.issn1556-6056
dc.identifier.urihttp://hdl.handle.net/2117/102823
dc.description.abstractCache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups.
dc.format.extent4 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors
dc.subject.lcshCache memory
dc.subject.otherMicroprocessor chips
dc.subject.otherCache storage
dc.titleExplaining dynamic cache partitioning speed ups
dc.typeArticle
dc.subject.lemacMicroprocessadors
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/L-CA.2007.3
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/4278824/
dc.rights.accessOpen Access
drac.iddocument654946
dc.description.versionPostprint (published version)
upcommons.citation.authorMoreto, M., Cazorla, F., Alex Ramirez, Valero, M.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE computer architecture letters
upcommons.citation.volume6
upcommons.citation.number1
upcommons.citation.startingPage1
upcommons.citation.endingPage4


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