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dc.contributor.authorSantana Jaria, Oliverio J.
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-03-23T11:44:52Z
dc.date.available2017-03-23T11:44:52Z
dc.date.issued2007-10
dc.identifier.citationSantana, O., Ramírez, A., Valero, M. Enlarging instruction streams. "IEEE transactions on computers", Octubre 2007, vol. 56, núm. 10, p. 1342-1357.
dc.identifier.issn0018-9340
dc.identifier.urihttp://hdl.handle.net/2117/102820
dc.description.abstractThe stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially containing multiple basic blocks, a stream. The long length of instruction streams makes it possible for the stream fetch engine to provide a high fetch bandwidth and to hide the branch predictor access latency, leading to performance results close to a trace cache at a lower implementation cost and complexity. Therefore, enlarging instruction streams is an excellent way to improve the stream fetch engine. In this paper, we present several hardware and software mechanisms focused on enlarging those streams that finalize at particular branch types. However, our results point out that focusing on particular branch types is not a good strategy due to Amdahl's law. Consequently, we propose the multiple-stream predictor, a novel mechanism that deals with all branch types by combining single streams into long virtual streams. This proposal tolerates the prediction table access latency without requiring the complexity caused by additional hardware mechanisms like prediction overriding. Moreover, it provides high-performance results which are comparable to state-of-the-art fetch architectures but with a simpler design that consumes less energy.
dc.format.extent16 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCompilers (Computer programs)
dc.subject.lcshMultiprocessors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherSuperscalar processor design
dc.subject.otherInstruction fetch
dc.subject.otherBranch prediction
dc.subject.otherAccess latency
dc.subject.otherCode optimization
dc.titleEnlarging instruction streams
dc.typeArticle
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.subject.lemacMultiprocessadors
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/TC.2007.70742
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/4302707/
dc.rights.accessOpen Access
drac.iddocument654939
dc.description.versionPostprint (published version)
upcommons.citation.authorSantana, O., Ramírez, A., Valero, M.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE transactions on computers
upcommons.citation.volume56
upcommons.citation.number10
upcommons.citation.startingPage1342
upcommons.citation.endingPage1357


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