Near-optimal loop tiling by means of cache miss equations and genetic algorithms
Tipo de documentoTexto en actas de congreso
Fecha de publicación2002
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condiciones de accesoAcceso abierto
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a code transformation targeted to reduce capacity misses. This paper presents a novel systematic approach to perform near-optimal loop tiling based on an accurate data locality analysis (cache miss equations) and a powerful technique to search the solution space that is based on a genetic algorithm. The results show that this approach can remove practically all capacity misses for all considered benchmarks. The reduction of replacement misses results in a decrease of the miss ratio that can be as significant as a factor of 7 for the matrix multiply kernel.
CitaciónAbella, J., González, A., Llosa, J., Vera, X. Near-optimal loop tiling by means of cache miss equations and genetic algorithms. A: International Conference on Parallel Processing Workshops. "International Conference on Parallel Processing Workshops: 18-21 August 2002, Vancouver, B.C., Canada: proceedings". Vancouver: Institute of Electrical and Electronics Engineers (IEEE), 2002, p. 568-577.
Versión del editorhttp://ieeexplore.ieee.org/document/1039779/