High-Performance low-vcc in-order core
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Power density grows in new technology nodes, thus requiring Vcc to scale especially in mobile platforms where energy is critical. This paper presents a novel approach to decrease Vcc while keeping operating frequency high. Our mechanism is referred to as immediate read after write (IRAW) avoidance. We propose an implementation of the mechanism for an Intel® SilverthorneTM in-order core. Furthermore, we show that our mechanism can be adapted dynamically to provide the highest performance and lowest energy-delay product (EDP) at each Vcc level. Results show that IRAW avoidance increases operating frequency by 57% at 500mV and 99% at 400mV with negligible area and power overhead (below 1%), which translates into large speedups (48% at 500mV and 90% at 400mV) and EDP reductions (0.61 EDP at 500mV and 0.33 at 400mV).
CitacióAbella, J., Chaparro, P., Vera, X., Carretero, J., González, A. High-Performance low-vcc in-order core. A: International Symposium on High-Performance Computer Architecture. "HPCA-16 2010: The Sixteenth International Symposium on High-Performance Computer Architecture". Bangalore: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 1-11.
Versió de l'editorhttp://ieeexplore.ieee.org/document/5416630/