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dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorErgin, Oguz
dc.contributor.authorVera Rivera, Francisco Javier
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-03-15T09:31:25Z
dc.date.available2017-03-15T09:31:25Z
dc.date.issued2006
dc.identifier.citationUnsal, O., Ergin, O., Vera, X., González, A. Empowering a helper cluster through data-width aware instruction selection policies. A: IEEE International Parallel and Distributed Processing Symposium. "Proceeding of the 20th IEEE International Parallel & Distributed Processing Symposium". Ixia, Rodes: IEEE Computer Society, 2006, p. 1-10.
dc.identifier.isbn1-42440054-6
dc.identifier.urihttp://hdl.handle.net/2117/102484
dc.description.abstractNarrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor back-end features. Those attributes can be combined synergistically to design special clusters operating on narrow values (a.k.a. helper cluster), potentially providing performance benefits. We complement a 32-bit monolithic processor with a low-complexity 8-bit helper cluster. Then, in our main focus, we propose various ideas to select suitable instructions to execute in the data-width based clusters. We add data-width information as another instruction steering decision metric and introduce new data-width based selection algorithms which also consider dependency, inter-cluster communication and load imbalance. Utilizing those techniques, the performance of a wide range of workloads are substantially increased; helper cluster achieves an average speedup of 11% for a wide range of 412 apps. When focusing on integer applications, the speedup can be as high as 22% on average
dc.format.extent10 p.
dc.language.isoeng
dc.publisherIEEE Computer Society
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors
dc.subject.otherWire
dc.subject.otherMicroarchitecture
dc.subject.otherComputer aided instruction
dc.subject.otherClustering algorithms
dc.subject.otherDelay effects
dc.subject.otherDecoding
dc.subject.otherProcessor scheduling
dc.subject.otherCosts
dc.subject.otherClocks
dc.titleEmpowering a helper cluster through data-width aware instruction selection policies
dc.typeConference report
dc.subject.lemacMicroprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/IPDPS.2006.1639350
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1639350/?reload=true&arnumber=1639350
dc.rights.accessOpen Access
local.identifier.drac2376419
dc.description.versionPostprint (published version)
local.citation.authorUnsal, O.; Ergin, O.; Vera, X.; González, A.
local.citation.contributorIEEE International Parallel and Distributed Processing Symposium
local.citation.pubplaceIxia, Rodes
local.citation.publicationNameProceeding of the 20th IEEE International Parallel & Distributed Processing Symposium
local.citation.startingPage1
local.citation.endingPage10


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