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Empowering a helper cluster through data-width aware instruction selection policies
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Ergin, Oguz |
dc.contributor.author | Vera Rivera, Francisco Javier |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-03-15T09:31:25Z |
dc.date.available | 2017-03-15T09:31:25Z |
dc.date.issued | 2006 |
dc.identifier.citation | Unsal, O., Ergin, O., Vera, X., González, A. Empowering a helper cluster through data-width aware instruction selection policies. A: IEEE International Parallel and Distributed Processing Symposium. "Proceeding of the 20th IEEE International Parallel & Distributed Processing Symposium". Ixia, Rodes: IEEE Computer Society, 2006, p. 1-10. |
dc.identifier.isbn | 1-42440054-6 |
dc.identifier.uri | http://hdl.handle.net/2117/102484 |
dc.description.abstract | Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor back-end features. Those attributes can be combined synergistically to design special clusters operating on narrow values (a.k.a. helper cluster), potentially providing performance benefits. We complement a 32-bit monolithic processor with a low-complexity 8-bit helper cluster. Then, in our main focus, we propose various ideas to select suitable instructions to execute in the data-width based clusters. We add data-width information as another instruction steering decision metric and introduce new data-width based selection algorithms which also consider dependency, inter-cluster communication and load imbalance. Utilizing those techniques, the performance of a wide range of workloads are substantially increased; helper cluster achieves an average speedup of 11% for a wide range of 412 apps. When focusing on integer applications, the speedup can be as high as 22% on average |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors |
dc.subject.other | Wire |
dc.subject.other | Microarchitecture |
dc.subject.other | Computer aided instruction |
dc.subject.other | Clustering algorithms |
dc.subject.other | Delay effects |
dc.subject.other | Decoding |
dc.subject.other | Processor scheduling |
dc.subject.other | Costs |
dc.subject.other | Clocks |
dc.title | Empowering a helper cluster through data-width aware instruction selection policies |
dc.type | Conference report |
dc.subject.lemac | Microprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/IPDPS.2006.1639350 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1639350/?reload=true&arnumber=1639350 |
dc.rights.access | Open Access |
local.identifier.drac | 2376419 |
dc.description.version | Postprint (published version) |
local.citation.author | Unsal, O.; Ergin, O.; Vera, X.; González, A. |
local.citation.contributor | IEEE International Parallel and Distributed Processing Symposium |
local.citation.pubplace | Ixia, Rodes |
local.citation.publicationName | Proceeding of the 20th IEEE International Parallel & Distributed Processing Symposium |
local.citation.startingPage | 1 |
local.citation.endingPage | 10 |