Empowering a helper cluster through data-width aware instruction selection policies
Visualitza/Obre
Cita com:
hdl:2117/102484
Tipus de documentText en actes de congrés
Data publicació2006
EditorIEEE Computer Society
Condicions d'accésAccés obert
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Abstract
Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor back-end features. Those attributes can be combined synergistically to design special clusters operating on narrow values (a.k.a. helper cluster), potentially providing performance benefits. We complement a 32-bit monolithic processor with a low-complexity 8-bit helper cluster. Then, in our main focus, we propose various ideas to select suitable instructions to execute in the data-width based clusters. We add data-width information as another instruction steering decision metric and introduce new data-width based selection algorithms which also consider dependency, inter-cluster communication and load imbalance. Utilizing those techniques, the performance of a wide range of workloads are substantially increased; helper cluster achieves an average speedup of 11% for a wide range of 412 apps. When focusing on integer applications, the speedup can be as high as 22% on average
CitacióUnsal, O., Ergin, O., Vera, X., González, A. Empowering a helper cluster through data-width aware instruction selection policies. A: IEEE International Parallel and Distributed Processing Symposium. "Proceeding of the 20th IEEE International Parallel & Distributed Processing Symposium". Ixia, Rodes: IEEE Computer Society, 2006, p. 1-10.
ISBN1-42440054-6
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