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dc.contributor.authorCodina Viñas, Josep M.
dc.contributor.authorSánchez Navarro, Jesús
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-03-15T09:16:18Z
dc.date.available2017-03-15T09:16:18Z
dc.date.issued2007
dc.identifier.citationCodina, J.M., Sánchez, J., González, A. Virtual cluster scheduling through the scheduling graph. A: International Symposium on Code Generation and Optimization. "International Symposium on Code Generation and Optimization, CGO 2007: 11-14 March 2007, San Jose, California". San Jose, CA: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 89-101.
dc.identifier.isbn978-0-7695-2764-2
dc.identifier.urihttp://hdl.handle.net/2117/102480
dc.description.abstractThis paper presents an instruction scheduling and cluster assignment approach for clustered processors. The proposed technique makes use of a novel representation named the scheduling graph which describes all possible schedules. A powerful deduction process is applied to this graph, reducing at each step the set of possible schedules. In contrast to traditional list scheduling techniques, the proposed scheme tries to establish relations among instructions rather than assigning each instruction to a particular cycle. The main advantage is that wrong or poor schedules can be anticipated and discarded earlier. In addition, cluster assignment of instructions is performed using another novel concept called virtual clusters, which define sets of instructions that must execute in the same cluster. These clusters are managed during the deduction process to identify incompatibilities among instructions. The mapping of virtual to physical clusters is postponed until the scheduling of the instructions has finalized. The advantages this novel approach features include: (1) accurate scheduling information when assigning, and, (2) accurate information of the cluster assignment constraints imposed by scheduling decisions. We have implemented and evaluated the proposed scheme with superblocks extracted from Speclnt95 and MediaBench. The results show that this approach produces better schedules than the previous state-of-the-art. Speed-ups are up to 15%, with average speed-ups ranging from 2.5% (2-Clusters) to 9.5% (4-Clusters).
dc.format.extent13 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherWorkstation clusters
dc.subject.otherInstruction sets
dc.subject.otherMultiprocessing systems
dc.subject.otherProcessor scheduling
dc.titleVirtual cluster scheduling through the scheduling graph
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/CGO.2007.39
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/4145107/
dc.rights.accessOpen Access
local.identifier.drac2395559
dc.description.versionPostprint (published version)
local.citation.authorCodina, J.M.; Sánchez, J.; González, A.
local.citation.contributorInternational Symposium on Code Generation and Optimization
local.citation.pubplaceSan Jose, CA
local.citation.publicationNameInternational Symposium on Code Generation and Optimization, CGO 2007: 11-14 March 2007, San Jose, California
local.citation.startingPage89
local.citation.endingPage101


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