Variable-based multi-module data caches for clustered VLIW processors
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Memory structures consume an important fraction of the total processor energy. One solution to reduce the energy consumed by cache memories consists of reducing their supply voltage and/or increase their threshold voltage at an expense in access time. We propose to divide the L1 data cache into two cache modules for a clustered VLIW processor consisting of two clusters. Such division is done on a variable basis so that the address of a datum determines its location. Each cache module is assigned to a cluster and can be set up as a fast power-hungry module or as a slow power-aware module. We also present compiler techniques in order to distribute variables between the two cache modules and generate code accordingly. We have explored several cache configurations using the Mediabench suite and we have observed that the best distributed cache organization outperforms traditional cache organizations by 19%-31% in energy-delay and by 11%-29% in energy-delay. In addition, we also explore a reconfigurable distributed cache, where the cache can be reconfigured on a context switch. This reconfigurable scheme further outperforms the best previous distributed organization by 3%-4%.
CitacióGibert, E., Abella, J., Sánchez, J., Vera, F.J., González, A. Variable-based multi-module data caches for clustered VLIW processors. A: International Conference on Parallel Architectures and Compilation Techniques. "PACT'05: 14th International Conference on Parallel Architectures and Compilation Techniques: 17-21 September 2005, St. Louis, Missouri". St. Louis, Missouri: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 207-217.
Versió de l'editorhttp://ieeexplore.ieee.org/document/1515594/