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dc.contributor.authorValero, Alejandro
dc.contributor.authorSahuquillo, Julio
dc.contributor.authorPetit, Salvador
dc.contributor.authorLorente, Vicente
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorLópez, Pedro
dc.contributor.authorDuato, José
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-11-08T09:07:38Z
dc.date.available2010-11-08T09:07:38Z
dc.date.created2009
dc.date.issued2009
dc.identifier.citationValero, A. [et al.]. An hybrid eDRAM/SRAM macrocell to implement first-level data caches. A: IEEE/ACM International Symposium on Microarchitecture. "42nd Annual IEEE/ACM International Symposium on Microarchitecture". Nova York: Association for Computing Machinery (ACM), 2009, p. 213-221.
dc.identifier.isbn978-1-60558-798-1
dc.identifier.urihttp://hdl.handle.net/2117/10159
dc.description.abstractSRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology, thus overcoming the speed limit of typical DRAM cells. In this paper we propose an n-bit macrocell that implements one static cell, and n-1 dynamic cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Our study shows that in a four-way set-associative cache with this macrocell compared to an SRAM based with the same capacity, leakage is reduced by about 75% and area more than half with a minimal impact on performance. Architectural mechanisms have also been devised to avoid refresh logic. Experimental results show that no performance is lost when the retention time is larger than 50K processor cycles. In addition, the proposed delayed writeback policy that avoids refreshing performs a similar amount of writebacks than a conventional cache with the same organization, so no power wasting is incurred.
dc.format.extent9 p.
dc.language.isoeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer storage devices
dc.subject.otherStatic and dynamic memory cells
dc.subject.otherRetention time
dc.subject.otherLeakage current
dc.titleAn hybrid eDRAM/SRAM macrocell to implement first-level data caches
dc.typeConference report
dc.subject.lemacOrdinadors -- Memòries
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1145/1669112.1669140
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac2377787
dc.description.versionPostprint (published version)
local.citation.authorValero, A.; Sahuquillo, J.; Petit, S.; Lorente, V.; Canal, R.; López, P.; Duato, J.
local.citation.contributorIEEE/ACM International Symposium on Microarchitecture
local.citation.pubplaceNova York
local.citation.publicationName42nd Annual IEEE/ACM International Symposium on Microarchitecture
local.citation.startingPage213
local.citation.endingPage221


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