Value prediction for speculative multithreaded architectures
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
The speculative multithreading paradigm (speculative thread-level parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitectures that adopt this paradigm strongly depends on the performance of the control and data speculation techniques. While control speculation is used to predict the most effective points where a thread can be spawned, data speculation is required to eliminate the serialization imposed by inter-thread dependences. This work studies the performance of different value predictors for speculative multithreaded processors. We propose a value predictor, the increment predictor, and evaluate its performance for a particular microarchitecture that implements this execution paradigm (Clustered Speculative Multithreaded architecture). The proposed trace-oriented increment predictor clearly outperforms trace-adapted versions of the last value, stride and context-based predictors, specially for small-sized history tables. A 1-KB increment predictor achieves a 73% prediction accuracy and a performance that is just 13% lower than that of a perfect value predictor.
CitacióMarcuello, P., Tubella, J., González, A. Value prediction for speculative multithreaded architectures. A: Annual IEEE/ACM International Symposium on Microarchitecture. "32nd Annual International Symposium on Microarchitecture: Haifa, Israel, November 16-18, 1999: proceedings". Haifa: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 230-236.
Versió de l'editorhttp://ieeexplore.ieee.org/document/809461/