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dc.contributor.authorMonreal Arnal, Teresa
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorGonzález González, José
dc.contributor.authorViñals Yufera, Víctor
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationMonreal, T., González, A., Valero, M., González, J., Viñals, V. Delaying physical register allocation trought virtual-physical registers. A: Annual IEEE/ACM International Symposium on Microarchitecture. "32nd Annual International Symposium on Microarchitecture: Haifa, Israel, November 16-18, 1999: proceedings". Haifa: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 186-192.
dc.description.abstractRegister file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper presents a novel physical register management scheme that allows for a late allocation (at the end of execution) of registers. We show that it can provide significant savings in number of registers and thus, it can significantly shorten the register file access time. The approach is based on virtual-physical registers, which we presented in a previous work, extended with a new register allocation policy. This policy consists of an on-demand allocation in order to maximize the register usage, combined with a stealing mechanism that prevents older instruction from being delayed by younger ones. This shortens the average number of cycles that each physical register is allocated, and allows for an early execution of instructions since they can obtain a physical register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in advance.
dc.format.extent7 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherParallel processing
dc.subject.otherPerformance evaluation
dc.subject.otherStorage management
dc.titleDelaying physical register allocation trought virtual-physical registers
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
upcommons.citation.authorMonreal, T.; González, A.; Valero, M.; González, J.; Viñals, V.
upcommons.citation.contributorAnnual IEEE/ACM International Symposium on Microarchitecture
upcommons.citation.publicationName32nd Annual International Symposium on Microarchitecture: Haifa, Israel, November 16-18, 1999: proceedings

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