A unified modulo scheduling and register allocation technique for clustered processors
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
This work presents a modulo scheduling framework for clustered ILP processors that integrates the cluster assignment, instruction scheduling and register allocation steps in a single phase. This unified approach is more effective than traditional approaches based on sequentially performing some (or all) of the three steps, since it allows optimizing the global code generation problem instead of searching for optimal solutions to each individual step. Besides, it avoids the iterative nature of traditional approaches, which require repeated applications of the three steps until a valid solution is found. The proposed framework includes a mechanism to insert spill code on-the-fly and heuristics to evaluate the quality of partial schedules considering simultaneously inter-cluster communications, memory pressure and register pressure. Transformations that allow trading pressure on a type of resource for another resource are also included. We show that the proposed technique outperforms previously proposed techniques. For instance, the average speed-up for the SPECfp95 is 36% for a 4-cluster configuration.
CitationCodina, J.M., Sánchez, F., González, A. A unified modulo scheduling and register allocation technique for clustered processors. A: International Conference on Parallel Architectures and Compilation Techniques. "2001 International Conference on Parallel Architectures and Compilation Techniques: 8-12 September 2001 Barcelona, Catalunya, Spain: proceedings". Barcelona: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 175-184.
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