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dc.contributor.authorMolina Clemente, Carlos
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.authorTubella Murgadas, Jordi
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-02-21T13:23:29Z
dc.date.available2017-02-21T13:23:29Z
dc.date.issued2005
dc.identifier.citationMolina, C., González, A., Tubella, J. Compiler analysis for trace-level speculative multithreaded architectures. A: Annual Workshop on Interaction between Compilers and Computer Architecture. "9th Annual Workshop on Interaction between Compilers and Computer Architecture: INTERACT'05: February 13, 2005, San Francisco, USA: proceedings". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 2-10.
dc.identifier.isbn0-7695-2321-8
dc.identifier.urihttp://hdl.handle.net/2117/101321
dc.description.abstractTrace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating on the result of several traces. The other thread executes speculated traces and verifies the speculation made by the first thread. In this paper, we propose a static program analysis for identifying candidate traces to be speculated. This approach identifies large regions of code whose live-output values may be successfully predicted. We present several heuristics to determine the best opportunities for dynamic speculation, based on compiler analysis and program profiling information. Simulation results show that the proposed trace recognition techniques achieve on average a speed-up close to 38% for a collection of SPEC2000 benchmarks.
dc.format.extent9 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCompilers (Computer programs)
dc.subject.lcshSimultaneous multithreading processors
dc.subject.otherBuildings
dc.subject.otherComputer architecture
dc.subject.otherData structures
dc.subject.otherFlow graphs
dc.subject.otherFrequency
dc.subject.otherInformation analysis
dc.subject.otherMicroarchitecture
dc.subject.otherPerformance analysis
dc.subject.otherRuntime
dc.subject.otherTesting
dc.titleCompiler analysis for trace-level speculative multithreaded architectures
dc.typeConference report
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/INTERACT.2005.6
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1423136/
dc.rights.accessOpen Access
drac.iddocument2376441
dc.description.versionPostprint (published version)
upcommons.citation.authorMolina, C.; González, A.; Tubella, J.
upcommons.citation.contributorAnnual Workshop on Interaction between Compilers and Computer Architecture
upcommons.citation.pubplaceSan Francisco
upcommons.citation.publishedtrue
upcommons.citation.publicationName9th Annual Workshop on Interaction between Compilers and Computer Architecture: INTERACT'05: February 13, 2005, San Francisco, USA: proceedings
upcommons.citation.startingPage2
upcommons.citation.endingPage10


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