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Compiler analysis for trace-level speculative multithreaded architectures
dc.contributor.author | Molina Clemente, Carlos |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Tubella Murgadas, Jordi |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-21T13:23:29Z |
dc.date.available | 2017-02-21T13:23:29Z |
dc.date.issued | 2005 |
dc.identifier.citation | Molina, C., González, A., Tubella, J. Compiler analysis for trace-level speculative multithreaded architectures. A: Annual Workshop on Interaction between Compilers and Computer Architecture. "9th Annual Workshop on Interaction between Compilers and Computer Architecture: INTERACT'05: February 13, 2005, San Francisco, USA: proceedings". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 2-10. |
dc.identifier.isbn | 0-7695-2321-8 |
dc.identifier.uri | http://hdl.handle.net/2117/101321 |
dc.description.abstract | Trace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating on the result of several traces. The other thread executes speculated traces and verifies the speculation made by the first thread. In this paper, we propose a static program analysis for identifying candidate traces to be speculated. This approach identifies large regions of code whose live-output values may be successfully predicted. We present several heuristics to determine the best opportunities for dynamic speculation, based on compiler analysis and program profiling information. Simulation results show that the proposed trace recognition techniques achieve on average a speed-up close to 38% for a collection of SPEC2000 benchmarks. |
dc.format.extent | 9 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Compilers (Computer programs) |
dc.subject.lcsh | Simultaneous multithreading processors |
dc.subject.other | Buildings |
dc.subject.other | Computer architecture |
dc.subject.other | Data structures |
dc.subject.other | Flow graphs |
dc.subject.other | Frequency |
dc.subject.other | Information analysis |
dc.subject.other | Microarchitecture |
dc.subject.other | Performance analysis |
dc.subject.other | Runtime |
dc.subject.other | Testing |
dc.title | Compiler analysis for trace-level speculative multithreaded architectures |
dc.type | Conference report |
dc.subject.lemac | Compiladors (Programes d'ordinador) |
dc.subject.lemac | Multiprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/INTERACT.2005.6 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1423136/ |
dc.rights.access | Open Access |
local.identifier.drac | 2376441 |
dc.description.version | Postprint (published version) |
local.citation.author | Molina, C.; González, A.; Tubella, J. |
local.citation.contributor | Annual Workshop on Interaction between Compilers and Computer Architecture |
local.citation.pubplace | San Francisco |
local.citation.publicationName | 9th Annual Workshop on Interaction between Compilers and Computer Architecture: INTERACT'05: February 13, 2005, San Francisco, USA: proceedings |
local.citation.startingPage | 2 |
local.citation.endingPage | 10 |