Compiler analysis for trace-level speculative multithreaded architectures
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Trace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating on the result of several traces. The other thread executes speculated traces and verifies the speculation made by the first thread. In this paper, we propose a static program analysis for identifying candidate traces to be speculated. This approach identifies large regions of code whose live-output values may be successfully predicted. We present several heuristics to determine the best opportunities for dynamic speculation, based on compiler analysis and program profiling information. Simulation results show that the proposed trace recognition techniques achieve on average a speed-up close to 38% for a collection of SPEC2000 benchmarks.
CitacióMolina, C., González, A., Tubella, J. Compiler analysis for trace-level speculative multithreaded architectures. A: Annual Workshop on Interaction between Compilers and Computer Architecture. "9th Annual Workshop on Interaction between Compilers and Computer Architecture: INTERACT'05: February 13, 2005, San Francisco, USA: proceedings". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 2-10.
Versió de l'editorhttp://ieeexplore.ieee.org/document/1423136/