On-line failure detection and confinement in caches
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need for continuous on-line testing techniques to cope with hard errors in the field. Similarly, those techniques are needed for detecting soft errors in logic, whose error rate is expected to raise in future technologies. Cache memories, which occupy most of the area of the chip, are typically protected with parity or ECC, but most of the wires as well as some combinational blocks remain unprotected against both soft and hard errors. This paper presents a set of techniques to detect and confine hard and soft errors in cache memories in combination with parity/ECC at very low cost. By means of hard signatures in data rows and error tracking, faults can be detected, classified properly and confined for hardware reconfiguration.
CitacióAbella, J., Chaparro, P., Vera, X., Carretero, J.S., González, A. On-line failure detection and confinement in caches. A: IEEE International On-Line Testing Symposium. "14th IEEE International On-Line Testing Symposium: Rhodes, Greece, July 6–9, 2008: proceedings". Rhodes: Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 3-9.
Versió de l'editorhttp://ieeexplore.ieee.org/document/4567052/