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The latency hiding effectiveness of decoupled access/execute processors
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-21T10:24:15Z |
dc.date.available | 2017-02-21T10:24:15Z |
dc.date.issued | 1998 |
dc.identifier.citation | Parcerisa, Joan-Manuel, Gonzalez, A. The latency hiding effectiveness of decoupled access/execute processors. A: EUROMICRO Conference. "24th EUROMICRO Conference: Västeras, Sweden, August 25-27, 1998: proceedings". Västeras: Institute of Electrical and Electronics Engineers (IEEE), 1998, p. 293-300. |
dc.identifier.isbn | 0-8186-8646-4 |
dc.identifier.uri | http://hdl.handle.net/2117/101283 |
dc.description.abstract | Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide-issue processors due to the increasing penalties that wire delays cause in the issue logic. The main target of out-of-order execution is to hide functional unit latencies and memory latency. However, the former can be quite effectively handled at compile time and this observation is one of the main arguments for the emerging EPIC architectures. In this paper, we demonstrate that a decoupled access/execute organization is very effective at hiding memory latency, even when it is very long. This paper presents a thorough evaluation of such processor organization. First, a generic decoupled access/execute architecture is defined and evaluated. Then the benefits of a lockup-free cache, control speculation and a store-load bypass mechanism under such an architecture are evaluated. Our analysis indicates that memory latency can be almost completely hidden by such techniques. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.lcsh | Cache memory |
dc.subject.other | Cache storage |
dc.subject.other | Delays |
dc.subject.other | Computer architecture |
dc.title | The latency hiding effectiveness of decoupled access/execute processors |
dc.type | Conference report |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/EURMIC.1998.711813 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/711813/ |
dc.rights.access | Open Access |
local.identifier.drac | 2328483 |
dc.description.version | Postprint (published version) |
local.citation.author | Parcerisa, Joan-Manuel; Gonzalez, A. |
local.citation.contributor | EUROMICRO Conference |
local.citation.pubplace | Västeras |
local.citation.publicationName | 24th EUROMICRO Conference: Västeras, Sweden, August 25-27, 1998: proceedings |
local.citation.startingPage | 293 |
local.citation.endingPage | 300 |