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Software-controlled operand-gating
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Smith, James E. |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-20T09:55:29Z |
dc.date.available | 2017-02-20T09:55:29Z |
dc.date.issued | 2004 |
dc.identifier.citation | Canal, R., González, A., Smith, J. Software-controlled operand-gating. A: International Symposium on Code Generation and Optimization. "Proceedings of the 2004 International Symposium on Code Generation and Optimization". California: IEEE Computer Society, 2004, p. 125-136. |
dc.identifier.isbn | 0-8695-2102-9 |
dc.identifier.uri | http://hdl.handle.net/2117/101209 |
dc.description.abstract | Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method for implementing software-controlled power gating is proposed and evaluated. The instruction set architecture (ISA) is enhanced to include opcodes that specify operand widths (if not already included in the ISA). A compiler or a binary translator uses statically available information to determine initial value ranges. The technique is enhanced through a profile-based analysis that results in the specialization of certain code regions for a given value range. After the analysis, instruction opcodes are assigned using the minimum required width. To evaluate this technique the Alpha instruction set is enhanced to include opcodes for 8, 16, and 32 bit operands. Applying the proposed software technique to the Speclnt95 benchmarks results in energy-delay savings of 14%. When combined with previously proposed hardware-based techniques, the energy-delay benefit is 28%. |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors -- Energy consumption |
dc.subject.lcsh | Compilers (Computer programs) |
dc.subject.other | Software performance evaluation |
dc.subject.other | Instruction sets |
dc.subject.other | Computer architecture |
dc.subject.other | Program compilers |
dc.title | Software-controlled operand-gating |
dc.type | Conference report |
dc.subject.lemac | Microprocessadors -- Consum d'energia |
dc.subject.lemac | Compiladors (Programes d'ordinador) |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/CGO.2004.1281669 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1281669/ |
dc.rights.access | Open Access |
local.identifier.drac | 2367769 |
dc.description.version | Postprint (published version) |
local.citation.author | Canal, R.; González, A.; Smith, J. |
local.citation.contributor | International Symposium on Code Generation and Optimization |
local.citation.pubplace | California |
local.citation.publicationName | Proceedings of the 2004 International Symposium on Code Generation and Optimization |
local.citation.startingPage | 125 |
local.citation.endingPage | 136 |