LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors
Tipo de documentoTexto en actas de congreso
Fecha de publicación2009
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condiciones de accesoAcceso abierto
The increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. non uniform cache architectures (NUCA) have been introduced to deal with this problem. This memory organization divides the whole memory space into smaller pieces or banks allowing nearer banks to have better access latencies than further banks. Moreover, an adaptive replacement policy that efficiently reduces misses in the last-level cache could boost performance, particularly if set associativity is adopted. Unfortunately, traditional replacement policies do not behave properly as they were designed for single-processors. This paper focuses on bank replacement. This policy involves three key decisions when there is a miss: where to place a data block within the cache set, which data to evict from the cache set and finally, where to place the evicted data. We propose a novel replacement technique that enables more intelligent replacement decisions to be taken. This technique is based on the observation that some types of data are less commonly accessed depending on which bank they reside in. We call this technique LRU-PEA (least recently used with a priority eviction approach). We show that the proposed technique significantly reduces the requests to the off-chip memory by increasing the hit ratio in the NUCA cache. This translates into an average IPC improvement of 8% and into an Energy per Instruction (EPI) reduction of 5%.
CitaciónLira, J., Molina, C., González, A. LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors. A: IEEE International Conference on Computer Design. "2009 IEEE International Conference on Computer Design: October 4-7, 2009, Resort at Squaw Creek, Lake Tahoe, CA". Lake Tahoe, CA: Institute of Electrical and Electronics Engineers (IEEE), 2009, p. 275-281.
Versión del editorhttp://ieeexplore.ieee.org/document/5413142/