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dc.contributor.authorJones, Timothy M.
dc.contributor.authorO’Boyle, Michael F.P.
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-02-16T14:32:34Z
dc.date.available2017-02-16T14:32:34Z
dc.date.issued2005
dc.identifier.citationJones, T., O’Boyle, M., Abella, J., Gonzalez, A. Software directed issue queue power reduction. A: International Symposium on High-Performance Computer Architecture. "HPCA-11 2005: 11th International Symposium on High-Performance Computer Architecture: 12-16 February 2005, San Francisco, California: proceedings". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 144-153.
dc.identifier.isbn0-7695-2275-0
dc.identifier.urihttp://hdl.handle.net/2117/101152
dc.description.abstractThe issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. In this paper we present a novel software assisted approach to power reduction where the processor dynamically resizes the issue queue based on compiler analysis. The compiler passes information to the processor about the number of entries needed which limits the number of instructions dispatched and resident in the queue. This saves power without adversely affecting performance. Compared with recently proposed hardware techniques, our approach is faster, simpler and saves more power. Using a simplistic scheme we achieve 47% dynamic and 31% static power savings in the issue queue with only a 2.2% performance loss. We then show that the performance loss can be reduced to less than 1.3% with 45% dynamic and 30% static power savings, outperforming all current approaches.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCompilers (Computer programs)
dc.subject.lcshMicroprocessors -- Energy consumption
dc.subject.otherParallel architectures
dc.subject.otherQueueing theory
dc.subject.otherProgram compilers
dc.titleSoftware directed issue queue power reduction
dc.typeConference report
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.subject.lemacMicroprocessadors -- Consum d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/HPCA.2005.32
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1385936/
dc.rights.accessOpen Access
local.identifier.drac2377459
dc.description.versionPostprint (published version)
local.citation.authorJones, T.; O’Boyle, M.; Abella, J.; Gonzalez, A.
local.citation.contributorInternational Symposium on High-Performance Computer Architecture
local.citation.pubplaceSan Francisco
local.citation.publicationNameHPCA-11 2005: 11th International Symposium on High-Performance Computer Architecture: 12-16 February 2005, San Francisco, California: proceedings
local.citation.startingPage144
local.citation.endingPage153


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