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Software directed issue queue power reduction
dc.contributor.author | Jones, Timothy M. |
dc.contributor.author | O’Boyle, Michael F.P. |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-16T14:32:34Z |
dc.date.available | 2017-02-16T14:32:34Z |
dc.date.issued | 2005 |
dc.identifier.citation | Jones, T., O’Boyle, M., Abella, J., Gonzalez, A. Software directed issue queue power reduction. A: International Symposium on High-Performance Computer Architecture. "HPCA-11 2005: 11th International Symposium on High-Performance Computer Architecture: 12-16 February 2005, San Francisco, California: proceedings". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 144-153. |
dc.identifier.isbn | 0-7695-2275-0 |
dc.identifier.uri | http://hdl.handle.net/2117/101152 |
dc.description.abstract | The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. In this paper we present a novel software assisted approach to power reduction where the processor dynamically resizes the issue queue based on compiler analysis. The compiler passes information to the processor about the number of entries needed which limits the number of instructions dispatched and resident in the queue. This saves power without adversely affecting performance. Compared with recently proposed hardware techniques, our approach is faster, simpler and saves more power. Using a simplistic scheme we achieve 47% dynamic and 31% static power savings in the issue queue with only a 2.2% performance loss. We then show that the performance loss can be reduced to less than 1.3% with 45% dynamic and 30% static power savings, outperforming all current approaches. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Compilers (Computer programs) |
dc.subject.lcsh | Microprocessors -- Energy consumption |
dc.subject.other | Parallel architectures |
dc.subject.other | Queueing theory |
dc.subject.other | Program compilers |
dc.title | Software directed issue queue power reduction |
dc.type | Conference report |
dc.subject.lemac | Compiladors (Programes d'ordinador) |
dc.subject.lemac | Microprocessadors -- Consum d'energia |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/HPCA.2005.32 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1385936/ |
dc.rights.access | Open Access |
local.identifier.drac | 2377459 |
dc.description.version | Postprint (published version) |
local.citation.author | Jones, T.; O’Boyle, M.; Abella, J.; Gonzalez, A. |
local.citation.contributor | International Symposium on High-Performance Computer Architecture |
local.citation.pubplace | San Francisco |
local.citation.publicationName | HPCA-11 2005: 11th International Symposium on High-Performance Computer Architecture: 12-16 February 2005, San Francisco, California: proceedings |
local.citation.startingPage | 144 |
local.citation.endingPage | 153 |