Mostra el registre d'ítem simple

dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-02-16T10:14:03Z
dc.date.available2017-02-16T10:14:03Z
dc.date.issued1993-03
dc.identifier.citationGonzález, A., Llaberia, J. Reducing branch delay to zero in pipelined processors. "IEEE transactions on computers", Març 1993, vol. 42, núm. 3, p. 363-371.
dc.identifier.issn0018-9340
dc.identifier.urihttp://hdl.handle.net/2117/101127
dc.description.abstractA mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with that of other schemes, and to analyze the performance of the mechanism with two alternative cache organizations.
dc.format.extent9 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCache memory
dc.subject.lcshComputer architecture
dc.subject.otherPipeline processing
dc.subject.otherBuffer storage
dc.subject.otherPerformance evaluation
dc.titleReducing branch delay to zero in pipelined processors
dc.typeArticle
dc.subject.lemacMemòria cau
dc.subject.lemacArquitectura d'ordinadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/12.210179
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/210179/
dc.rights.accessOpen Access
local.identifier.drac1651629
dc.description.versionPostprint (published version)
local.citation.authorGonzález, A.; Llaberia, J.
local.citation.publicationNameIEEE transactions on computers
local.citation.volume42
local.citation.number3
local.citation.startingPage363
local.citation.endingPage371


Fitxers d'aquest items

Thumbnail

Aquest ítem apareix a les col·leccions següents

Mostra el registre d'ítem simple