Reducing wire delay penalty through value prediction
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
In this paper we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating the prediction locally where the value is produced. Only in the case of misprediction, the long wire delay is experienced. We apply this concept to a clustered microarchitecture in order to reduce inter-cluster communication. The predictability of values provides the dynamic instruction partitioning hardware with less constraints to optimize the trade-off between communication requirements and workload balance, which is the most critical issue of the partitioning scheme. We show that value prediction reduces the penalties caused by inter-cluster communication by 18% on average for a realistic implementation of a 4-cluster microarchitecture.
CitacióParcerisa, J.M., González, A. Reducing wire delay penalty through value prediction. A: Annual IEEE/ACM International Symposium on Microarchitecture. "33rd Annual ACM/IEEE International Symposium on Microarchitecture: MICRO-33, 2000: 10-13 december 2000: Monterey, California, USA: proceedings". Monterey, California: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 317-326.
Versió de l'editorhttp://ieeexplore.ieee.org/document/898081/