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dc.contributor.authorGarcía Flores, Víctor
dc.contributor.authorRico Carro, Alejandro
dc.contributor.authorVillavieja Prados, Carlos
dc.contributor.authorCarpenter, Paul M.
dc.contributor.authorNavarro, Nacho
dc.contributor.authorRamirez, Alex
dc.date.accessioned2017-02-13T13:44:30Z
dc.date.available2017-05-02T00:30:42Z
dc.date.issued2016-04-29
dc.identifier.citationGarcia, V., Rico, A., Villavieja, C., Carpenter, P., Navarro, N., Ramirez, A. Adaptive runtime-assisted block prefetching on chip-multiprocessors. "International journal of parallel programming", 29 Abril 2016, p. 1-21.
dc.identifier.issn0885-7458
dc.identifier.urihttp://hdl.handle.net/2117/100924
dc.description.abstractMemory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution.
dc.format.extent21 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCache memory
dc.subject.otherCache memories
dc.subject.otherPrefetch
dc.subject.otherTask based programming models
dc.titleAdaptive runtime-assisted block prefetching on chip-multiprocessors
dc.typeArticle
dc.subject.lemacMemòria cau
dc.subject.lemacGestió de memòria (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1007/s10766-016-0431-8
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://link.springer.com/article/10.1007%2Fs10766-016-0431-8
dc.rights.accessOpen Access
drac.iddocument18741148
dc.description.versionPostprint (author's final draft)
upcommons.citation.authorGarcia, V., Rico, A., Villavieja, C., Carpenter, P., Navarro, N., Ramirez, A.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameInternational journal of parallel programming
upcommons.citation.startingPage1
upcommons.citation.endingPage21


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