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dc.contributor.authorAragón, Juan Luis
dc.contributor.authorGonzález González, José
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-02-10T12:21:00Z
dc.date.available2017-02-10T12:21:00Z
dc.date.issued2006-03
dc.identifier.citationAragón, J., González, J., González, A. Control speculation for energy-efficient next-generation superscalar processors. "IEEE transactions on computers", Març 2006, vol. 55, núm. 3, p. 281-291.
dc.identifier.issn0018-9340
dc.identifier.urihttp://hdl.handle.net/2117/100841
dc.description.abstractConventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, increasing front-end energy and issue queue utilization and, thus, wasting around 30 percent of the power dissipated by a processor. Furthermore, processor design trends lead to increasing clock frequencies by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. As next-generation high-performance processors become deeply pipelined, the amount of wasted energy due to misspeculated instructions will go up. The aim of this work is to reduce the energy consumption of misspeculated instructions. We propose selective throttling, which triggers different power-aware techniques (fetch throttling, decode throttling, or disabling the selection logic) depending on the branch prediction confidence level. Results show that combining fetch-bandwidth reduction along with select-logic disabling provides the best performance in terms of overall energy reduction and energy-delay product improvement (14 percent and 10 percent, respectively, for a processor with a 22-stage pipeline and 16 percent and 13 percent, respectively, for a processor with a 42-stage pipeline).
dc.format.extent11 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors -- Energy consumption
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherControl speculation
dc.subject.otherEnergy-aware systems
dc.subject.otherLow-power design
dc.subject.otherProcessor architecture
dc.titleControl speculation for energy-efficient next-generation superscalar processors
dc.typeArticle
dc.subject.lemacMicroprocessadors -- Consum d'energia
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/TC.2006.32
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1583558
dc.rights.accessOpen Access
local.identifier.drac1660381
dc.description.versionPostprint (published version)
local.citation.authorAragón, J.; González, J.; González, A.
local.citation.publicationNameIEEE transactions on computers
local.citation.volume55
local.citation.number3
local.citation.startingPage281
local.citation.endingPage291


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