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A cost-effective clustered architecture
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-10T10:23:14Z |
dc.date.available | 2017-02-10T10:23:14Z |
dc.date.issued | 1999 |
dc.identifier.citation | Canal, R., Parcerisa, J.M., González, A. A cost-effective clustered architecture. A: International Conference on Parallel Architectures and Compilation Techniques. "1999 International Conference on Parallel Architectures and Compilation Techniques: October 12-16, 1999, Newport Beach, California: proceedings". Newport Beach, California: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 160-168. |
dc.identifier.isbn | 0-7695-0425-6 |
dc.identifier.uri | http://hdl.handle.net/2117/100821 |
dc.description.abstract | In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute simple integer instructions. With minor hardware modifications to a conventional superscalar processor, the issue width can potentially be doubled without increasing the hardware complexity. In fact, the result is a clustered architecture with two heterogeneous clusters. We propose to extend this architecture with a dynamic steering logic that sends the instructions to either cluster. The performance of clustered architectures depends on the inter-cluster communication overhead and the workload balance. We present a scheme that uses run-time information to optimise the trade-off between these figures. The evaluation shows that this scheme can achieve an average speed-up of 35% over a conventional 8-way issue (4 int+4 fp) machine and that it outperforms the previously proposed one. |
dc.format.extent | 9 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.other | Floating point arithmetic |
dc.subject.other | Parallel architectures |
dc.subject.other | Parallel machines |
dc.subject.other | Performance evaluation |
dc.subject.other | Resource allocation |
dc.title | A cost-effective clustered architecture |
dc.type | Conference report |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/PACT.1999.807517 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=807517 |
dc.rights.access | Open Access |
local.identifier.drac | 2328485 |
dc.description.version | Postprint (published version) |
local.citation.author | Canal, R.; Parcerisa, Joan-Manuel; González, A. |
local.citation.contributor | International Conference on Parallel Architectures and Compilation Techniques |
local.citation.pubplace | Newport Beach, California |
local.citation.publicationName | 1999 International Conference on Parallel Architectures and Compilation Techniques: October 12-16, 1999, Newport Beach, California: proceedings |
local.citation.startingPage | 160 |
local.citation.endingPage | 168 |