A cost-effective clustered architecture
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute simple integer instructions. With minor hardware modifications to a conventional superscalar processor, the issue width can potentially be doubled without increasing the hardware complexity. In fact, the result is a clustered architecture with two heterogeneous clusters. We propose to extend this architecture with a dynamic steering logic that sends the instructions to either cluster. The performance of clustered architectures depends on the inter-cluster communication overhead and the workload balance. We present a scheme that uses run-time information to optimise the trade-off between these figures. The evaluation shows that this scheme can achieve an average speed-up of 35% over a conventional 8-way issue (4 int+4 fp) machine and that it outperforms the previously proposed one.
CitationCanal, R., Parcerisa, J.M., González, A. A cost-effective clustered architecture. A: International Conference on Parallel Architectures and Compilation Techniques. "1999 International Conference on Parallel Architectures and Compilation Techniques: October 12-16, 1999, Newport Beach, California: proceedings". Newport Beach, California: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 160-168.
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