On reducing register pressure and energy in multiple-banked register files
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. We present a novel technique to reduce register requirements as well as their dynamic and static power dissipation that is based on delaying the dispatch of instructions while minimizing its impact on performance. The proposed technique outperforms previous schemes in both performance and power savings. With only 1.77% IPC loss, the mechanism achieves more than 13% dynamic and 15% static extra power savings in the integer rename buffers and more than 9% dynamic and 10% static extra power savings in the FP rename buffers. Significant power savings are also achieved if the processor uses a physical register file for both committed and noncommitted values instead of rename buffers. Additionally the register requirements are reduced by more than 18% and 13% for integer and FP programs respectively.
CitacióAbella, J., González, A. On reducing register pressure and energy in multiple-banked register files. A: IEEE International Conference on Computer Design. "Proceedings 21st International Conference on Computer Design". San Jose, California: Institute of Electrical and Electronics Engineers (IEEE), 2003, p. 14-20.
Versió de l'editorhttp://ieeexplore.ieee.org/document/1240867/