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dc.contributor.authorGibert Codina, Enric
dc.contributor.authorSánchez, Jesús
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-02-01T13:35:25Z
dc.date.available2017-02-01T13:35:25Z
dc.date.issued2005-10
dc.identifier.citationGibert, E., Sánchez, J., González, A. Distributed data cache designs for clustered VLIW processors. "IEEE transactions on computers", Octubre 2005, vol. 54, núm. 10, p. 1227-1241.
dc.identifier.issn0018-9340
dc.identifier.urihttp://hdl.handle.net/2117/100462
dc.description.abstractWire delays are a major concern for current and forthcoming processors. One approach to deal with this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a local register file and a subset of the functional units, while the L1 data cache typically remains centralized in What we call partially distributed architectures. However, as technology evolves, the relative latency of such a centralized cache will increase, leading to an important impact on performance. In this paper, we propose partitioning the L1 data cache among clusters for clustered VLIW processors. We refer to this kind of design as fully distributed processors. In particular; we propose and evaluate three different configurations: a snoop-based cache coherence scheme, a word-interleaved cache, and flexible LO-buffers managed by the compiler. For each alternative, instruction scheduling techniques targeted to cyclic code are developed. Results for the Mediabench suite'show that the performance of such fully distributed architectures is always better than the performance of a partially distributed one with the same amount of resources. In addition, the key aspects of each fully distributed configuration are explored.
dc.format.extent15 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors -- Design and construction
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshCache memory
dc.subject.otherSingle data stream architectures
dc.subject.otherDesign styles
dc.titleDistributed data cache designs for clustered VLIW processors
dc.typeArticle
dc.subject.lemacMicroprocessadors -- Disseny i construcció
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacMemòria cau
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/TC.2005.163
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1501789
dc.rights.accessOpen Access
local.identifier.drac1642596
dc.description.versionPostprint (published version)
local.citation.authorGibert, E.; Sánchez, J.; González, A.
local.citation.publicationNameIEEE transactions on computers
local.citation.volume54
local.citation.number10
local.citation.startingPage1227
local.citation.endingPage1241


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