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Distributed data cache designs for clustered VLIW processors
dc.contributor.author | Gibert Codina, Enric |
dc.contributor.author | Sánchez, Jesús |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-01T13:35:25Z |
dc.date.available | 2017-02-01T13:35:25Z |
dc.date.issued | 2005-10 |
dc.identifier.citation | Gibert, E., Sánchez, J., González, A. Distributed data cache designs for clustered VLIW processors. "IEEE transactions on computers", Octubre 2005, vol. 54, núm. 10, p. 1227-1241. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/100462 |
dc.description.abstract | Wire delays are a major concern for current and forthcoming processors. One approach to deal with this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a local register file and a subset of the functional units, while the L1 data cache typically remains centralized in What we call partially distributed architectures. However, as technology evolves, the relative latency of such a centralized cache will increase, leading to an important impact on performance. In this paper, we propose partitioning the L1 data cache among clusters for clustered VLIW processors. We refer to this kind of design as fully distributed processors. In particular; we propose and evaluate three different configurations: a snoop-based cache coherence scheme, a word-interleaved cache, and flexible LO-buffers managed by the compiler. For each alternative, instruction scheduling techniques targeted to cyclic code are developed. Results for the Mediabench suite'show that the performance of such fully distributed architectures is always better than the performance of a partially distributed one with the same amount of resources. In addition, the key aspects of each fully distributed configuration are explored. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors -- Design and construction |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.lcsh | Cache memory |
dc.subject.other | Single data stream architectures |
dc.subject.other | Design styles |
dc.title | Distributed data cache designs for clustered VLIW processors |
dc.type | Article |
dc.subject.lemac | Microprocessadors -- Disseny i construcció |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/TC.2005.163 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1501789 |
dc.rights.access | Open Access |
local.identifier.drac | 1642596 |
dc.description.version | Postprint (published version) |
local.citation.author | Gibert, E.; Sánchez, J.; González, A. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 54 |
local.citation.number | 10 |
local.citation.startingPage | 1227 |
local.citation.endingPage | 1241 |
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