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dc.contributor.authorRanjan, Rakesh
dc.contributor.authorMarcuello Pascual, Pedro
dc.contributor.authorLatorre Salinas, Fernando
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-10-28T08:36:07Z
dc.date.available2010-10-28T08:36:07Z
dc.date.created2009-12-16
dc.date.issued2009-12-16
dc.identifier.citationRanjan, R. [et al.]. P-slice based efficient speculative multithreading. A: International Conference on High Performance Computing. "16th International Conference on High Performance Computing". Kochi: IEEE Computer Society Publications, 2009, p. 119-128.
dc.identifier.urihttp://hdl.handle.net/2117/10039
dc.description.abstractMicroprocessor industry has recently shifted towards multi-core to take advantage of the ever increasing number of transistors provided by the new technologies. Unfortunately, the multi-core approach does not allow single threaded applications to benefit from the additional cores to improve their execution time. Speculative multithreading (SpMT) has been proposed in the past to boost performance of irregular applications in multi-core environments. In this work, we study the main bottlenecks of these architectures, such as the memory behavior and the pre-computation slices and propose two novel schemes that allow SpMT to get 25% average speedup over single threaded execution. We propose Selective Replication as a technique to improve the performance of the SpMT memory system. This technique does not introduce additional traffic in the bus and improves the performance of a conventional SpMT memory model by 6% on average and up to 21% for some applications. Also, we propose a scheme called Slice Specialization that reduces the number of instructions in the pre-computation slices by adapting the slice to every single speculative thread spawned. The later proposal outperforms previous schemes with slices by 15% and overall, both techniques combined achieve an improvement of 20% over a conventional SpMT processor.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherIEEE Computer Society Publications
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshSimultaneous multithreading processors
dc.subject.otherMultithreading
dc.subject.otherSpeculation
dc.subject.otherTLS
dc.titleP-slice based efficient speculative multithreading
dc.typeConference report
dc.subject.lemacMicroprocessadors
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/HIPC.2009.5433216
dc.rights.accessOpen Access
drac.iddocument2396875
dc.description.versionPostprint (published version)
upcommons.citation.authorRanjan, R.; Marcuello, P.; Latorre, F.; González, A.
upcommons.citation.contributorInternational Conference on High Performance Computing
upcommons.citation.pubplaceKochi
upcommons.citation.publishedtrue
upcommons.citation.publicationName16th International Conference on High Performance Computing
upcommons.citation.startingPage119
upcommons.citation.endingPage128


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