Mostra el registre d'ítem simple

dc.contributor.authorCabrera, Daniel
dc.contributor.authorMartorell Bofill, Xavier
dc.contributor.authorGaydadjiev, Georgi
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorJiménez González, Daniel
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-10-27T14:08:22Z
dc.date.available2010-10-27T14:08:22Z
dc.date.created2009-07
dc.date.issued2009-07
dc.identifier.citationCabrera, D. [et al.]. OpenMP extensions for FPGA Accelerators. A: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. "2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation". Samos: 2009, p. 17-24.
dc.identifier.isbn978-1-4244-4501-1
dc.identifier.urihttp://hdl.handle.net/2117/10025
dc.description.abstractReconfigurable computing is one of the paths to explore towards low-power supercomputing. However, programming these reconfigurable devices is not an easy task and still requires significant research and development efforts to make it really productive. In addition, the use of these devices as accelerators in multicore, SMPs and ccNUMA architectures adds an additional level of programming complexity in order to specify the offloading of tasks to reconfigurable devices and the interoperability with current shared-memory programming paradigms such as OpenMP. This paper presents extensions to OpenMP 3.0 that try to address this second challenge and an implementation in a prototype runtime system. With these extensions the programmer can easily express the offloading of an already existing reconfigurable binary code (bitstream) hiding all the complexities related with device configuration, bitstream loading, data arrangement and movement to the device memory. Our current prototype implementation targets the SGI Altix systems with RASC blades (based on the Virtex 4 FPGA). We analyze the overheads introduced in this implementation and propose a hybrid host/device operational mode to hide some of these overheads, significantly improving the performance of the applications. A complete evaluation of the system is done with a matrix multiplication kernel, including an estimation considering different FPGA frequencies.
dc.format.extent8 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshAdaptive computing systems
dc.subject.otherApplication program interfaces
dc.subject.otherBinary codes
dc.subject.otherField programmable gate arrays
dc.subject.otherHardware description languages
dc.subject.otherMatrix multiplication
dc.subject.otherMessage passing
dc.subject.otherOpen systems
dc.subject.otherParallel programming
dc.subject.otherShared memory systems
dc.titleOpenMP extensions for FPGA Accelerators
dc.typeConference report
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ICSAMOS.2009.5289237
dc.rights.accessOpen Access
local.identifier.drac2358847
dc.description.versionPostprint (published version)
local.citation.authorCabrera, D.; Martorell, X.; Gaydadjiev, G.; Ayguade, E.; Jimenez, D.
local.citation.contributorInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
local.citation.pubplaceSamos
local.citation.publicationName2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
local.citation.startingPage17
local.citation.endingPage24


Fitxers d'aquest items

Thumbnail

Aquest ítem apareix a les col·leccions següents

Mostra el registre d'ítem simple