Mostra el registre d'ítem simple

dc.contributor.authorLópez de Buen, Víctor Fernando Ubaldo
dc.date.accessioned2008-03-11T16:51:08Z
dc.date.available2008-03-11T16:51:08Z
dc.date.issued1987
dc.identifier.citationLópez de Buen, Víctor Fernando Ubaldo. "Multistage interconnection networks in multiprocessor systems. A simulation study". Qüestió. 1987, vol. 11, núm. 3
dc.identifier.issn0210-8054 (versió paper)
dc.identifier.urihttp://hdl.handle.net/2099/4576
dc.description.abstractThe principal modelling and simulation features of multistage interconnection networks operating in packet switching are discussed in this paper. The networks studied interconnect processors and memory modules in multiprocessor systems. Several methods are included to increase the bandwidth achievable with this kind of networks. Besides using network buffering, the possibility of having queues of requests at the memory modules is considered. Network conflicts can be reduced using a second network to return requests from memory modules. The connection of more than one processor or memory module to each of the multistage network input or output lines allows the interconnection of large multiprocessor systems using small multistage networks. This is implemented using a single shared bus connection. The effective bandwidth of these networks is compared to that of circuit switching multistage networks and Crossbar. Simulations results reflect an important improvement in network performance.
dc.format.extent73-86 p.
dc.language.isoeng
dc.publisherUniversitat Politècnica de Barcelona. Centre de Càlcul
dc.rightsAttribution-NonCommercial-NoDerivs 2.5 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/2.5/es/
dc.subject.lcshComputing Methodologies.
dc.subject.otherInterconnection networks
dc.subject.otherPerformance analysis
dc.subject.otherPacket communication
dc.subject.otherMultiprocessor systems
dc.subject.otherSimulation
dc.titleMultistage interconnection networks in multiprocessor systems. A simulation study
dc.title.alternativeRedes de interconexión multiestado en sistemas multiprocesadores. Un estudio de simulación
dc.typeArticle
dc.subject.lemacInformàtica
dc.subject.lemacCiències de la computació
dc.description.peerreviewedPeer Reviewed
dc.subject.amsClassificació AMS::68 Computer science::68U Computing methodologies and applications
dc.rights.accessOpen Access
local.personalitzacitaciotrue


Fitxers d'aquest items

Thumbnail

Aquest ítem apareix a les col·leccions següents

Mostra el registre d'ítem simple