Systolic architectures for fuzzy processing and their simulation

Abstract

This paper details the study of systolic architectures for fuzzy rules processing made at the Hardware and Advanced Control Laboratory - INTA. The theoretical basis of these architectures is described and analysed. Likewise, the resultant schematics are simulated using a hardware description language (VHDL) with standard cells from ES2. This gives us a very accurate assessment of their real performance. In this way we can detect the inherent shortcomings in this class of systems and we outline several ways of overcoming then.