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dc.contributor.authorMarkovic, Nikola
dc.contributor.authorNemirovsky, Daniel
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorCristal Kestelman, Adrián
dc.date.accessioned2015-06-02T13:52:39Z
dc.date.available2015-06-02T13:52:39Z
dc.date.issued2015-05-05
dc.identifier.citationMarkovic, Nikola [et al.]. Hardware scheduling algorithms for asymmetric single-ISA CMPs. A: "BSC Doctoral Symposium (2nd: 2015: Barcelona)". 2nd ed. Barcelona: Barcelona Supercomputing Center, 2015, p. 75.
dc.identifier.urihttp://hdl.handle.net/2099/16543
dc.description.abstractAs thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. Since more and more applications become multi-threaded we expect to find a growing number of threads executing on a machine. Consequently, the operating system will require increasingly larger amounts of CPU time to schedule these threads efficiently. Instead of perpetuating the trend of performing more complex thread scheduling in the operating system, we propose a two lightweight hardware thread scheduling mechanisms. First is a Hardware Round-Robin Scheduling (HRRS) policy which is influenced by Fairness Scheduling techniques thereby reducing thread serialization and improving parallel thread performance. Second is a Thread Lock Section-aware Scheduling (TLSS) policy which extends HRRS policy. TLSS policy is influenced by the Fairness-aware Scheduling and bottleneck identification techniques. It complements the HRRS scheduler by identifying multithreaded application bottlenecks such as thread synchronization sections. We show that HRRS outperforms Fairness scheduler by 17 percent while TLSS outperforms HRRS by 11 percent on an ACMP consisted of one large (out-of-order) core and three small (in-order) cores.
dc.format.extent1 p.
dc.language.isoeng
dc.publisherBarcelona Supercomputing Center
dc.relation.ispartofBSC Doctoral Symposium (2nd: 2015: Barcelona)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing
dc.subject.lcshSupercomputers
dc.subject.lcshParallel processing (Electronic computers)
dc.titleHardware scheduling algorithms for asymmetric single-ISA CMPs
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.subject.lemacSupercomputadors
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.rights.accessOpen Access
local.identifier.drac25532640
local.citation.authorMarkovic, Nikola; Nemirovsky, Daniel; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián
local.citation.pubplaceBarcelona
local.citation.publicationNameBSC Doctoral Symposium (2nd: 2015: Barcelona)
local.citation.startingPage75
local.citation.endingPage75
local.citation.edition2nd


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