System co-simulation interfacing an instruction set simulator with systemc
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hdl:2099.1/9540
Tipus de documentProjecte/Treball Final de Carrera
Data2008-01-29
Condicions d'accésAccés obert
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Reconeixement-NoComercial-CompartirIgual 2.5 Espanya
Abstract
During the last years, the productivity of digital electronic systems has not been
able to keep pace with Moore’s Law, which announces that the number of
transistors incorporated in an integrated circuit increases twofold every two
years.
I
n addition to this growth in terms of complexity, the current characteristics of
the market as well as the ever-increasing cost of electronic systems
development and production are squeezing the micro-electronic industry that
longs to find a solution.
With the advent of Transaction Level Modelling (TLM), a new level of
abstraction, and SystemC, an open source system level description language,
the industry has found a new breakthrough in system development by means
of an earlier architecture exploration of a system and an earlier development of
the software.
Co-simulation of hardware and software also takes advantage of SystemC
language and TLM, making easy and faster the integration of this two
platforms, being the most common approach the use of SystemC to model the
hardware and an Instruction Set Simulator (ISS) to model software part.
I
n this thesis an approach to interface an ISS with a SystemC model is
described in order to achieve compatibility and extensibility between hardware
and software, and with the ultimate goal of constructing models of complex
systems.
TitulacióENGINYERIA TÈCNICA DE TELECOMUNICACIÓ, ESPECIALITAT EN SISTEMES DE TELECOMUNICACIÓ (Pla 2000)
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memoria.pdf | memòria | 270,7Kb | Visualitza/Obre |