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Beehive: an FPGA-based multiprocessor architecture
dc.contributor | Cristal Kestelman, Adrián |
dc.contributor.author | Arcas Abella, Oriol |
dc.date.accessioned | 2009-09-30T07:08:54Z |
dc.date.available | 2009-09-30T07:08:54Z |
dc.date.issued | 2009-09-23 |
dc.identifier.uri | http://hdl.handle.net/2099.1/7460 |
dc.description.abstract | In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for studying computer architecture because of its flexibility and low cost. However, users of software simulators must choose between high performance and high fidelity emulation. This project presents an FPGA-based multiprocessor architecture to speed up multiprocessor architecture research and ease parallel software simulation. |
dc.language.iso | eng |
dc.publisher | Universitat Politècnica de Catalunya |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject.lcsh | Microprocessors |
dc.subject.lcsh | Integrated circuits |
dc.subject.other | Multiprocessador |
dc.subject.other | FPGA |
dc.subject.other | Simulació |
dc.subject.other | Emulació |
dc.subject.other | BEE3 |
dc.subject.other | Beehive |
dc.subject.other | Honeycomb |
dc.subject.other | Plasma |
dc.subject.other | Multiprocessor |
dc.title | Beehive: an FPGA-based multiprocessor architecture |
dc.type | Master thesis |
dc.subject.lemac | Microprocessadors |
dc.subject.lemac | Circuits integrats |
dc.identifier.slug | 59395 |
dc.rights.access | Open Access |
dc.date.updated | 2009-09-29T11:46:39Z |
dc.audience.educationlevel | Màster |
dc.audience.mediator | Facultat d'Informàtica de Barcelona |
dc.audience.degree | MÀSTER UNIVERSITARI EN TECNOLOGIES DE LA INFORMACIÓ (Pla 2006) |