Master's degree in Electronic Engineering (MEE)
Recent Submissions
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Izhikevich neural model and STDP learning algorithm mapping on spiking neural network hardware emulator
(Universitat Politècnica de Catalunya, 2020-11-15)
Master thesis
12 months embargoFrom the 20th century, biological mechanisms of the brain behaviour have become more and more interesting for the research communities in information fields due to the computational power of the systems they inspire. In ... -
Design, implementation, and validation of probability distributions generators in FPGA
(Universitat Politècnica de Catalunya, 2021-05-25)
Master thesis
Restricted access - confidentiality agreement -
Design of a clock and data recovery circuit in FDSOI technology for high speed serial links
(Universitat Politècnica de Catalunya, 2021-03)
Master thesis
Open AccessThe purpose of this thesis is to design an 8 Gbps clock and data recovery circuit intended to work in the receiver of a high-speed Serializer-Deserializer interface (SerDes). The proposed architecture is based on a ... -
Design for Testability methodologies applied to a RISC-Vprocessor
(Universitat Politècnica de Catalunya, 2021-01-29)
Master thesis
Open AccessThe decrease in the size of transistors and technology nodes has made manufacturing processes increasingly difficult and unreliable, Design for Test techniques provide measures to thoroughly test the manufactured device ... -
Graphene biosensors
(Universitat Politècnica de Catalunya, 2020-09)
Master thesis
Open AccessThe transmittance of graphene films over insulating substrates at Terahertz (THz) frequencies is analysed with the aim of characterizing its conductivity using a frequency domain THz spectrometer. Graphene is a candidate ... -
Approximate arithmetic units under voltage under-scaling
(Universitat Politècnica de Catalunya, 2021-01-28)
Master thesis
Open AccessIncreasingly power hungry processors and the identification of error tolerant applications have made approximate computing techniques one of the researching scopes of the present. The main objective of this work is to study ... -
Physical implementation of an industrial design using a 180nm technology
(Universitat Politècnica de Catalunya, 2020-01)
Master thesis
Open AccessThis thesis has been developed at Monolithic Power Systems; an IC design company located in Barcelona. The objective of the thesis is to learn the physical flow and make the tape out of a real-life project. One part of the ... -
Impact of physical low power techniques in a RISC-V processor
(Universitat Politècnica de Catalunya, 2021-01-28)
Master thesis
Open AccessPower consumption is one of the main aspects in the overall performance of en electronic circuit. Design for low power can be applied from algorithm through the physical implementation of the integrated circuit. In this ... -
Continuous Test Integration by reader-Multi Card Holder
(Universitat Politècnica de Catalunya, 2020-01)
Master thesis
Restricted access - confidentiality agreement -
Analysing of high power ups(30 /40KVA and 60/80 KVA) ups Cube 4 family & designing an electronic card adaptor for low power (10 and 20 KVA) UPS cube 4 family
(Universitat Politècnica de Catalunya, 2020-10)
Master thesis
Open AccessAn Uninterruptible Power Supply (UPS) is an electrical system that gives a load with power when an input fails and meanwhile, increase its efficiency and performance. Nowadays, UPS is growing fast within the industrial ... -
Design of an Output Interface for an In-Memory-Computing CNN Accelerator
(Universitat Politècnica de Catalunya, 2020-11-27)
Master thesis
Open AccessAnalog in-memory computing accelerators are one of the most promising solutions to reduce data movement limitations in deep neural networks (DNNs). While analog in-memory computing accelerators have been studied in many ... -
In-memory-computing CNN accelerator employing charge-domain compute
(Universitat Politècnica de Catalunya, 2020-11)
Master thesis
Open AccessHigh-dimensional matrix-vector-multiplications (MVM) are the main operations of deep neural networks (DNN). As the size of DNNs increases, data movement becomes a problem and limits their performance. Analog in-memory ...
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