Document typeMaster thesis
Rights accessOpen Access
The aim of this master's thesis is to elasticize Esterel. Esterel is an imperative hardware description language (HDL) used to describe reactive systems, and oriented to specify control systems. It belongs to the family of synchronous languages, and it allows to describe causality, concurrency and interruptions. Elastic circuits preserve a protocol that makes it possible for the circuit to be latency-insensitive. Besides, elastic circuits are easy to implement and can be synthesized automatically. The goal of the thesis is to provide an automatic synthesis method of elastic circuits from Esterel specifications. At the semantic level, it is proven that the generated elastic circuits are functionally equivalent to the conventional circuits generated using Esterel V7 compiler.