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dc.contributorCortadella, Jordi
dc.contributorSapatnekar, Sachin
dc.contributor.authorAlvarez Ruiz, Alex
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics
dc.date.accessioned2014-10-17T11:27:00Z
dc.date.available2014-10-17T11:27:00Z
dc.date.issued2014-07
dc.identifier.urihttp://hdl.handle.net/2099.1/23111
dc.description.abstractTechnology mapping is the task to transform a technology independent logic network into a mapped network using gates from a library, optimizing some objective function such total area, delay or power consumption. As stated, the problem is completely intractable. Therefore, different techniques are applied to solve the problem, such as using different simplified representations. The usual approach consists of using a fixed library, typically partially handmade. Designing such libraries is a costly process, specially because of the lack of good automatic techniques to perform it. This is the main motivation for this work and the goal is to move from fixed-library technology mapping to library-free technology mapping. This thesis presents different algorithms and techniques to move to library-free technology mapping for area and for delay optimization
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Matemàtiques i estadística::Matemàtica discreta
dc.subject.lcshAlgorithms
dc.subject.otherAlgorithms
dc.subject.otherTechnology mapping
dc.subject.otherGraphs
dc.subject.otherOptimization
dc.titleLibrary-free technology mapping for VLSI circuits with regular layouts
dc.typeMaster thesis
dc.subject.lemacAlgorismes
dc.subject.amsClassificació AMS::68 Computer science::68W Algorithms
dc.identifier.slugFME-1001
dc.rights.accessOpen Access
dc.date.updated2014-07-18T04:28:35Z
dc.audience.educationlevelMàster
dc.audience.mediatorUniversitat Politècnica de Catalunya. Facultat de Matemàtiques i Estadística


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