A large-scale spiking neural networks emulation architecture
Document typeMaster thesis
Rights accessOpen Access
The purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a large-scale SNN emulator. It preserves the basic hardware structure of SNAVA, making however several changes to optimize the performance. In particular, SNAVA+ project focuses on the aim to exploit more efficiently the availables resources, to reduce both the area and power consumption of the FPGA. A better use of the resources, in fact, is the main key to increase the potentiality of the SNN emulator, i.e. to increase the number of neurons and synapses simulated.
DegreeMÀSTER UNIVERSITARI EN ENGINYERIA DE TELECOMUNICACIÓ (Pla 2013)