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dc.contributorNemirovsky, Mario
dc.contributorMoreto Planas, Miquel
dc.contributor.authorRoca Marí, Damián
dc.date.accessioned2014-10-07T12:13:17Z
dc.date.available2014-10-07T12:13:17Z
dc.date.issued2014-07-01
dc.identifier.urihttp://hdl.handle.net/2099.1/22855
dc.description.abstractWe have developed a new kind of simulator based in queue models and statistical methods. It allows a fast and accurate simulation. It is really useful to perform a really fast design space exploration. We have validated the model against a real chip, Intel Ivy Bridge Processor
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer architecture
dc.subject.otherSimulació
dc.subject.otherTeoria de cues
dc.subject.otherMetodes estadístics
dc.subject.otherProcessador
dc.subject.otherArquitectura de Computadors
dc.subject.otherSimulation
dc.subject.otherQueue models
dc.subject.otherstatistical methods
dc.subject.otherprocessor
dc.subject.othercomputer architecture
dc.titleHigh level queuing architecture model for high-end processors
dc.typeMaster thesis
dc.subject.lemacArquitectura d'ordinadors
dc.identifier.slug100728
dc.rights.accessOpen Access
dc.date.updated2014-07-15T04:00:24Z
dc.audience.educationlevelMàster
dc.audience.mediatorFacultat d'Informàtica de Barcelona


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