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dc.contributorNemirovsky, Mario
dc.contributorSolé Pareta, Josep
dc.contributor.authorRoca Marí, Damián
dc.description.abstract[ANGLÈS] Computers, and multicore processors in specific, need cache memory to improve memory bandwidth and overall performance. There are different types of cache (private and shared) divided into different levels of hierarchy. Keeping coherence and consistency of shared values in these caches is a major performance bottleneck on multicore systems. To address this issue, there are several protocols that invalidate or update these values when a core needs to modify them. But these protocols require broadcast communication (or similar) that in today NoCs represents a big cost in terms of cycles. In order to improve this bottleneck, the first step in this research is to know and have an approximation of the target that represents these invalidations in the terms of performance of the system. To obtain that estimation is mandatory to use programs or simulators of a real process inside a multicore/multithreaded processor to visualize the communications between these cores and the effects of sharing a part of the space address. The reason is that these invalidations are produced by keeping the coherence between different copies of the same variable (shared space). Once that we have a simulator that allows us to see the communications we can make different configurations to emulate a real processor in different scenarios. With these cases, we can obtain how the number of invalidations is modified depending on the parameters of the system (number of cores, size of cache memories, etc) and the applications which are running. Due to this, the results can vary for different applications since each of them uses the shared memory space in a different way. With this information we can elaborate some statistics to extract the first conclusions and fix the bases for future work. These results also enables us to study the scalability of the actual models to see what would happen if we have more than 1000-core processor because the actual simulators do not support such high number of cores.
dc.description.abstract[CASTELLÀ] Los chips multicore conforman la realidad en el campo de los computadores. Pero dichos sistemas presentan muchos problemas que restringen su potencial. En este proyecto se realiza un estudio del principal, el sistema de memoria y mas concretamente, la memoria cache. Se estudia la escalibilidad que presentan las soluciones actuales con respecto al número de cores y se extraen las conclusiones pertinentes.
dc.description.abstract[CATALÀ] La tendència actual quant a processadors consisteix a integrar múltiples cores dins d'un mateix xip. Són coneguts com a xips multicore (CMP), però el seu diseny està ple de problemes. En aquest projecte s'estudien, centrant-se en el sistema de memoria i més concretament en la memòria cau. En cocnret, s'analitza el funcionament dels protocols de coherència i la seva escalabilitat respecte el nombre de cores. Finalment, s'extreuen les conclusions que les solucions actuals no serveixen per a un nombre de cores elevat.
dc.publisherUniversitat Politècnica de Catalunya
dc.rightsS'autoritza la difusió de l'obra mitjançant la llicència Creative Commons o similar 'Reconeixement-NoComercial- SenseObraDerivada'
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCache memory
dc.subject.otherchip multicore
dc.subject.othermemory system
dc.subject.othercoherence protocols
dc.subject.othersistema de memoria
dc.subject.otherprotocolos de coherencia
dc.subject.otherchips multicore
dc.subject.otherarquitectura d'ordinadors
dc.titleCommunication bottelneck analysis on big data applications
dc.title.alternativeAnálisis de los bottlenecks en comunicaciones en aplicaciones de big data
dc.title.alternativeAnàlisi dels bottlenecks a les comunicacions en aplicacions de big data
dc.typeMaster thesis (pre-Bologna period)
dc.subject.lemacMemòria cau
dc.rights.accessOpen Access
dc.audience.educationlevelEstudis de primer/segon cicle
dc.audience.mediatorEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona
dc.audience.degreeENGINYERIA DE TELECOMUNICACIÓ (Pla 1992)

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