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dc.contributorCarmona Vargas, Josep
dc.contributorCortadella, Jordi
dc.contributor.authorSan Pedro Martín, Javier de
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics
dc.date.accessioned2012-07-20T14:18:33Z
dc.date.available2012-07-20T14:18:33Z
dc.date.issued2012-06-22
dc.identifier.urihttp://hdl.handle.net/2099.1/15846
dc.description.abstractToday, even the simplest laptop processor has at least four cores and a graphics card containing tens of cores. It is not hard to find more performance- oriented processors with hundreds of cores, and it is expected to see processors with thousands of cores in the not very far future. In these and future processors, the design of the interconnection network between the cores and the memory subsystem is a key design aspect. Simple topologies like buses or rings provide great e fficiency, but do not scale as good as meshes once the number of cores increases. We explore the use of hierarchical network designs as an alternative, where diff erent topologies are stacked in a single network. The lowest layers use rings or buses, taking advantage of locality, while other layers use meshes or more complex topologies. To fully explore these and other chip multiprocessor design aspects, we build an interconnection network simulator that is capable of simulating arbitrary hierarchies of multiple network topologies. We propose using parameterizable automata as tra ffic sources, as a trade-off between full processor simulation and simulation using purely random traffic. By altering the automaton high-level parameters, changes in the processor workload can be simulated, such as the expected average memory tra ffic, the locality of the memory accesses, the additional traffi c caused by diff erent cache coherency protocols, etc.
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.rightsAttribution-NonCommercial-ShareAlike 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshMultiprocessors
dc.subject.lcshNetworks on a chip
dc.titleA Simulation framework for hierarchical Network-on-Chip systems
dc.typeMaster thesis
dc.subject.lemacMultiprocessadors
dc.subject.lemacSistemes incrustats (Informàtica)
dc.rights.accessOpen Access
dc.audience.educationlevelMàster
dc.audience.mediatorFacultat d'Informàtica de Barcelona
dc.audience.degreeMÀSTER UNIVERSITARI EN COMPUTACIÓ (Pla 2006)


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